This invention relates to an amplification circuit, particularly to an amplification circuit used in a voltage comparison circuit of a chopper type or an auto-zero-sampled data type.
With the developments in integrated analog circuits such as integrated analog-digital conversion circuits, etc., high performance is required for a voltage comparison circuit incorporated in such a circuit. Among the characteristics in such a voltage comparison circuit, greater importance is attached to high speed response characteristics, offsetless characteristics and high resolution characteristics.
In FIG. 1 there is shown a conventional voltage comparison circuit called a chopper or auto-zero-sampled data type comparison circuit. This type of voltage comparison circuit comprises two n-channel MOS transistors TR1 and TR2, one end of each of which is connected to one electrode of a capacitor C1, wherein the other end of the former is connected to a voltage input terminal VI1 and that of the latter is connected to the other voltage terminal VI2, respectively, and an amplification circuit whose input terminal is connected to the other electrode of the capacitor C1. This amplification circuit comprises an inverting amplifier 3 and an n-channel MOS transistor TR3 connected between input and output terminals of the inverting amplifier 3.
Clock signals CP1, CP2 and CP3 are fed to the gates of the n-channel MOS transistors TR1, TR2, and TR3, respectively. Further, there is a parasitic capacitor CS2 between gate and drain of the MOS transistor TR3, and a parasitic capacitor CS3 between the input and output terminals of the inverting amplifier 3.
An example of an application of the voltage comparison circuit shown in FIG. 1, for example, is disclosed in the "A Monolithic Charge-Balancing Successive Approximation A/D Technique" by Thomas P. Redfern et al IEEE Journal, Solid-State Circuit, Vol. SC-14, pp 912-920, Dec. 1979.
Each of operation cycles of the voltage comparison circuit shown in FIG. 1 is, as shown in FIG. 2A, divided into a period for setting operation point and a voltage comparison period. Initially, at each starting time of the operation point setting period of respective operating cycles, as shown in FIG. 2B, a first clock signal CP1 is set to a high level, a second clock signal CP2 is held, as shown in FIG. 2C, at a low level, and a third clock signal CP3 is set to a high level, as shown in FIG. 2D.
In this case, in response to the third clock signal CP3 the MOS transistor TR3 becomes conductive, the input and the output terminals of the inverting amplifier 3 are short-circuited through the MOS transistor TR3, and the potentials at the input and output terminals of the inverting amplifier 3 are converged to an inversion threshold voltage value VTH.
At the same time in response to the first clock signal CP1 the MOS transistor TR1 is rendered conductive and an input voltage V1 at the input terminal VI1 is applied to the capacitor C1 through the MOS transistor to charge the capacitor C1.
Next, during this operation point setting period, at first the third clock signal CP3 is set to a low level, and following to this, the first clock signal CP1 is set to the low level. These clock signals CP1 and CP3 are held at the low level for the following voltage comparison period. Further, at the starting time of this voltage comparison period, the second clock signal CP2 is set to the high level.
According to the above described operation, the MOS transistor TR2 becomes conductive and an input voltage V2 is applied to the capacitor C1 through this MOS transistor TR2.
In consequence a voltage corresponding to a voltage difference VD between the input voltage V1 and the input voltage V2 is applied to the input terminal of the inverting amplifier 3, and from the inverting amplifier 3 an output voltage corresponding to this voltage difference is obtained.
Now suppose that the voltage difference VD between the input voltages V1 and V2 in the preceding operation cycle is, for example, as shown in FIG. 2E, a positive value such as +10 mV and it changes to a negative value, for example, -3 mV in the succeeding cycle. At the starting time of the operation point setting period in the succeeding operation cycle, when the third clock signal CP3 is set to the high level (not shown in FIG. 2D) there is included a ripple component in this third clock signal CP3, and the ripple component is transmitted to the input and output terminals of the inverting amplifier 3 through the parasitic capacitors CS1 and CS2 by a feed through effect, respectively.
In consequence the potential at the input terminal of the inverting amplifier 3, as shown in FIG. 2F, converges to the threshold voltage value VTH while fluctuating around the threshold voltage value.
When the ripple component in the high level of the third clock signal CP3 is superposed on the input voltage of the inverting amplifier 3, the inverting amplifier 3 inverts this high level input voltage. Accordingly, an output voltage V3 of this inverting amplifier 3 is reduced sharply, as shown in FIG. 2G, to the low level.
The output voltage V3 reduced to the low level is superposed on the input voltage of the inverting amplifier 3 through the parasitic capacitor CS3 by a feed through effect.
Consequently, this input voltage becomes lower than the threshold voltage value VTH, and the inverting amplifier 3 inverts the low level input voltage and generates a high level output voltage.
A similar inverting-amplifying operation by the inverting amplifier 3 is repeatedly carried out. This inverting-amplifying operation by the amplifier 3 is repeatedly carried out until the input voltage becomes equal to the inversion threshold voltage value VTH. But the operation point setting period is limited to a predetermined length, so that at the completion time of this operation point setting period, that is, at the starting time of the voltage comparison period, an offset voltage VOS with respect to the inverse threshold voltage value VTH is applied to the input terminal of the inverting amplifier 3, undesirably influencing the voltage comparison operation. In other words, in the voltage comparison period, the time in which the output voltage of the inverting amplifier 3 converges to a voltage level corresponding to the voltage difference VD between the input voltages V1 and V2 becomes longer.
A broken line shown in FIG. 2G is an output voltage which will be generated by the inverting amplifier 3, when the third clock signal CP3 containing no ripple component is set to the high level. In this case the output voltage of the inverting amplifier 3 is quickly inverted to approach the threshold voltage value VTH, and during the voltage comparison period it approaches a voltage corresponding to the voltage difference VD, and quickly becomes equal to the threshold voltage value VTH.
Conventionally, many attempts have been proposed in which size of the third MOS transistor TR3 is enlarged to reduce ON resistance, that is, to reduce the resistance of the transistor in the conductive state so that an input voltage to the inverting amplifier 3 can be quickly set close to the inversion threshold voltage value during the operation point setting period, and/or size of an MOS transistor composing the inverting amplifier 3 is enlarged to increase the gain of the inverting amplifier 3.
However, enlarging the size of the third MOS transistor TR3 results in an increase in the parasitic capacitances CS1 and CS2, and also enlarging the size of the MOS transistor constituting the inverting amplifier 3 causes an increase in the parasitic capacitance CS3. Thus, the input voltage of the inverting amplifier 3 is prevented from quickly becoming equal to the inversion threshold voltage value VTH.
Thus, conventionally, in order to set the input voltage for the inverting amplifier 3 equal to the inversion threshold voltage value VTH in the operation point setting period, it is required to lengthen the operation point setting period, lowering the operation speed. When the operation setting period is set short, the comparison operation will be initiated before an input voltage to the inverting amplifier 3 sufficiently converges with the inversion threshold VTH undesirably lowering comparison resolution.